E852 Trigger Specs

Trigger Documents and Diagrams 1997

  • Trigger timing relative to S2
  • Busy/Deadtime logic, overall conceptual diagram
  • Busy/Deadtime logic with CsI and upstream beamtune
  • Busy/Deadtime logic with DAQ busy and TCYL Auxillary Trigger
  • DAQ interface
  • DEA logic
  • Drift chamber clock control logic
  • Level 1 trigger mlu logic
  • Level 1 prescaler logic
  • Strobes derived from pretrigger
  • Level 2 trigger mlu logic 1997
  • Level 2 NIM logic for final trigger 1997
  • Level 2A and 2B prescaler logic 1997
  • Level 2 strobes 1997
  • LGD logic in hut, part 1
  • LGD logic in hut, part 2
  • S counters and EV/BV and Cerenkov input to pretrigger 1997
  • S counters and Cerenkov input to fast trailer 1997
  • S5 logic
  • Pretrigger 1997
  • Pretrigger Deadtime 1997
  • Pulser trigger
  • TDC connections
  • TCYL logic plus misc control signals for DEA ADC, TDC
  • Tcyl 1997
  • Tcyl multiplicity logic 1997
  • H9C9 logic 1997
  • c9_mirror_numbering 1997
  • RAM logic, 1997
  • RAM strobes 1997
  • Delta T 1997